Solid state imagers reproduce an image by converting photons to signals that are representative of the image. In an imager, photosensors capture the photons and convert them to electrical charges which are read and used to represent the image. Each photosensor may include a photodiode, which is initially reset and then allowed to accumulate charges during an integration period. The accumulated charge is proportional to the light intensity of the image and may be represented by a pixel image voltage, Vsig. In complementary metal-oxide-semiconductor (CMOS) imagers, each pixel also produces a reset voltage, Vrst. CMOS imagers often perform correlated double sampling (CDS) to generate a pixel output signal representative of the difference between the pixel reset voltage Vrst and the pixel image voltage Vsig. For example, one of the voltages may be subtracted from the other using an up-down counter, though this is generally possible only if the imager includes an integrating analog-to-digital converter (ADC), such as a single-slope analog-to-digital converter.
Single-slope analog-to-digital converters in a column parallel pixel array readout architecture have benefits such as reliable monotonicity and relatively simple circuits and controllers. However, single-slope analog-to-digital converters are also characterized by a relatively slow conversion speed, especially for high resolution applications. For a typical digital single lens reflection (DSLR) camera, a resolution of at least 12-14 bits is often necessary to effectively perform many image enhancement operations, such as tone reproduction, gamma correction, etc. The up/down counters of the single-slope analog-to-digital converters each count from 0 to 16383, which is 214−1, to achieve 14-bit resolution. If the operating frequency of the single-slope analog-to-digital converters is 50 MHz, for example, one conversion takes approximately (16 k* 1/50 MHz)=320 microseconds (μs) to complete. This is usually not acceptable for a DSLR application imager that requires a high frame rate for video output, such as 30 frames per second (fps). Moreover, digital correlated double sampling technology requires two analog-to-digital conversions, resulting in a total analog-to-digital conversion time of 640 μs, which is usually not acceptable. For example, 640 μs*2000 rows=1.3 seconds per frame, or 0.77 fps, which is much less than the 30 fps requirement mentioned above.
Digital correlated double sampling has superior characteristics over conventional analog correlated double sampling. Because the correlated double sampling is executed in the digital domain, noise which may be introduced by the correlated double sampling circuit may no longer exist. Because the differentiation operation is conducted after the all analog signal processing is executed (e.g., gain amplification, analog-to-digital conversion), the offset caused by the analog components can be corrected. The column fixed pattern noise associated with conventional correlated double sampling techniques requires embedded digital memory such as SRAM to store all column offset values to be subtracted. To enable a high frame rate and low noise level, a new digital correlated double sampling architecture that is suited to the fast analog-to-digital conversion mechanism is needed.
Thus, systems and methods are needed that address one or more of the aforementioned shortcomings of conventional correlated double sampling techniques using column parallel readout.
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